The present invention pertains generally to computing systems. More specifically, the present invention relates to a providing access to shared resources in a computing system such as multi-processor computer systems and the like. More particularly, techniques for prediction of the time between two consecutive memory accesses are described.
In a basic computer system, a central processing unit, or CPU, operates in accordance with a pre-determined program or set of instructions stored within an associated memory. In addition to the stored instruction set or program under which the processor operates, memory space, either within the processor memory or in an associated additional memory, is provided to facilitate the central processor""s manipulation of information during processing. The additional memory provides for the storage of information created by the processor as well as the storage of information on a temporary, or xe2x80x9cscratchpadxe2x80x9d, basis which the processor uses in order to carry out the program. In addition, the associated memory provides locations in which output information from the processor""s operating set of instructions is placed in order to be available for the system""s output device(s).
In systems in which many components (processors, hard drive, etc) must share a common bus in order to access memory there is a high probability of memory access conflicts. Especially in the case of multiprocessor computer systems, and the like, in which different processors are simultaneously in operation, access to memory or other shared resources becomes complex. Since it is likely that each of the processors or processor systems may require access to the same memory simultaneously, conflicts between processors will generally be unavoidable. Essentially, the operation of two or more processors or processor systems periodically results in overlap of the memory commands with respect to a common memory, or other shared resource, in the multi-processor computer system.
Conventional approaches to solving the problem of conflicting memory access requests to a shared memory include, in one case, complete redundancy of the memories used for each of the processors, and isolation of the processor systems. However, this approach to solving the problem of conflicting memory access requests often defeats the intended advantage of the multiple processor system. Such multiple processor systems are most efficient if operated in such a manner as to provide parallel computing operations upon the same data in which one processor supports the operation of the other. Conventionally, such processor systems may be either time shared in which the processors compete for access to a shared resource, such as memory, or the processor systems may be dual ported in which each processor has its own memory bus, for example, where one is queued while the other is given access.
Various approaches have been used to avoid the above described conflict problems. In one approach, the avoidance of conflicts is accomplished by sequentially operating the processors or by time sharing the processors. In this way, the processors simply xe2x80x9ctake turnsxe2x80x9d accessing the shared resource in order to avoid conflict. Such systems commonly include xe2x80x9cpassing the ringxe2x80x9d or xe2x80x9ctoken systemsxe2x80x9d in which the potentially conflicting processors are simply polled by the system in accordance with a pre-determined sequences similar to passing a ring about a group of users.
Unfortunately, use of sequential processor access methodologies imposes a significant limitation upon the operation of the overall computer system. This limitation arises from the fact that a substantial time is used by the system in polling the competing processors. In addition, in the case where only a single processor is operating and requires access to the shared memory, for example, a delay occurs whenever the processor accesses the shared resource following each memory cycle as the system steps through the access sequence.
Another conventional approach to conflict avoidance relies upon establishing priorities amongst the processors in the computer system. One such arrangement provides every processor assigned to it a priority of system importance. The memory controller simply provides access to the highest priority processor every time a conflict occur. For example, in a two processor system, a first and a second processor access a shared memory which is typically a dynamic RAM (DRAM) type memory device which requires periodic refreshing of the memory maintain stored data. Generally, the DRAM type memory is refreshed by a separate independent refresh system. In such a multi-processor system, both the processors and the refresh system compete for access to the common memory. A system memory controller will process memory access request conflicts, or commands, as determined by the various priorities assigned to the processors and the refresh system. While such systems resolve conflicts and are somewhat more efficient than pure sequential conflict avoidance systems, they still suffer from lack of flexibility.
Another approach to conflict resolution involves decision-making capabilities incorporated in the memory controller. Unfortunately, because the decision making portions of the memory controller are operated under the control and timing of a clock system, a problem arises in that substantial time is utilized in performing the actual decision making before the memory controller can grant access to the common memory.
Unfortunately, this problem of performing the actual decision making substantially erodes the capability of conventional memory controllers granting access to multi-bank type memory systems. In multi-bank type memory systems, the actual memory core is departmentalized into specific regions, or banks, in which data to be retrieved is stored. Although providing faster and more efficient memory access, the complexity required of conventional memory controllers in coping with a multi-bank memory device substantially slows the overall access time of the system as a whole.
In view of the foregoing, it should be apparent that a method of speeding up a memory access of a memory page included in a memory bank in a multi-bank type memory by a memory controller is desired.
According to the present invention, techniques for prediction of the time between two consecutive memory accesses are described. In one embodiment, a method for very fast calculation of the earliest command issue time for a new command issued by a memory controller is disclosed. The memory controller includes N page status registers each of which includes four page timers such that each of the page timers store a period of time between a last issued command to the particular page and a predicted next access to the memory, wherein the next access to the same page can be xe2x80x9cclosexe2x80x9d, xe2x80x9copenxe2x80x9d, xe2x80x9cwritexe2x80x9d or xe2x80x9creadxe2x80x9d. An incoming new command is received and it is then determined how long a particularly page access has to wait before the issue. An appropriate contents of a command timing lookup table is selected by the new command. A new time value is written into appropriate page timers that has to be inserted between the new command and a possible next access to the same page. In a preferred embodiment, the resolution of the page timers is approximately one clock cycle such that a data timing lookup table stores time indicates how cycles after the issue of the new command that data on a data bus will be valid.
A further understanding of the nature and advantages of the present invention may be realized by reference to the remaining portions of the specification and the drawings.